The present disclosure generally relates to interconnections between compute nodes of a symmetric multiprocessing (SMP) system. In particular, this disclosure relates to maintaining data flow between two computing nodes while replacing a faulty cable connected between the nodes.
An SMP system is a tightly coupled computing system having a pool of two or more homogeneous processors that share a centralized “main memory” (MM), and operate under a single operating system. In an SMP system, the pool of homogeneous processors can each run independently, each processor executing different programs and working on different data, and having access to shared system resources, including memory, input/output (I/O) devices, and interrupt systems. The homogeneous processors can be interconnected using a system bus or a crossbar switch. Each processor can have an associated, private, high-speed cache memory to accelerate the MM data access and to reduce the system bus traffic.